This invention relates to a PNPN semiconductor switch utilized as talking circuit switches of a telephone exchange or the like.
For the purpose of description, a prior art PNPN semiconductor switch will firstly be outlined with reference to FIGS. 1A and 1B of the accompanying drawings. The switch comprises a P type diffused region 1 acting as an anode region, a P type diffused region 2 acting as a P gate region, an N type diffused region 3 acting as a cathode region and the source region of an MOSFET, an N type diffused region 4 acting as the drain region of the MOSFET, an anode electrode 5, an anode terminal 5', a cathode electrode 6, a cathode terminal 6', a gate electrode 7 connected to have the same potential as the anode electrode 5, a polycrystalline silicon electrode 8 acting as the gate electrode of the MOSFET, a resistor 9 formed of the polycrystalline silicon electrode 8, a P gate electrode 10 interconnecting the diffused regions 2 and 4 and one end of the resistor 9, an N type substrate 16, a semiinsulating layer 12 disposed on the entire surface of the substrate 16 except over the P type diffused regions 1 and 2, and an insulating layer 11 disposed over the semiinsulating layer 12. A portion of the P type diffused region 2 forms a resistor 111 and an electrode 112 is provided to cause one end of the resistor 111 to have the same potential as the cathode electrode 6. A capacitor C.sub.1 is formed between the gate electrode 7 and the polycrystalline silicon electrode 8, while a capacitor C.sub.2 is formed between the polycrystalline silicon electrode 8 and the diffused regions 2, 3 and 4.
This PNPN semiconductor switch can prevent a misoperation when applied voltage builds up steeply, and can be formed as an integrated circuit which is driven by light. When the PNPN semiconductor switch is driven by current, the electrode 10 acts as a P gate electrode.
When a rapidly building up voltage which supplies a positive bias to the anode electrode 5 and a negative bias to the cathode electrode 6 is applied to this PNPN semiconductor switch, a transient current flows through a PN junction formed between the P type diffused region 2 and the N type substrate 16. However, since the potential of the polycrystalline silicon electrode 8 rises to a potential determined by the capacitances of the capacitors C.sub.1 and C.sub.2 at the same time that an input voltage is applied, electrons would forms an N channel between the N type diffused regions 3 and 4. Accordingly, the current generated at the PN junction and flowing through the P type diffused region 2 will flow toward the cathode electrode 6 via the P gate electrode 10, the N type diffused region 4, the N channel described above and the N type diffused region 3 with the result that the PNPN element constituted by the P type diffused region 1, the N type substrate 16, the P type diffused region 2 and the N type diffused region 3 does not act as a switching element and shows a high dv/dt capability.
Since it is possible to control the charge and discharge of the potential of the polycrystalline silicon electrode 8 with the resistor 9 and the capacitors C.sub.1 and C.sub.2, it is possible to cause the PNPN switching element to operate as described above only for an input voltage which builds up steeply but the switch does not operate as described above for a DC voltage or a low frequency input voltage supplied during normal operation. Thus, since the operating potential of the polycrystalline silicon electrode 8 is the same as that of the P type diffused region 2, to operate the PNPN element by light irradiation, the element must be operated at a photocurrent corresponding to the gate sensitivity determined by the resistor 111 formed in the P type diffused region 2.
However, there is a definite limit for the gate sensitivity of the PNPN element.
As shown in FIG. 1A, since the resistor 111 is formed by using a portion of the P type diffused region 2, it is impossible to make the resistance value of resistor 111 high. If the resistance value is increased, the capacitance at the PN junction formed between the resistor 111 and the N type substrate 16 increases, thus forming a new factor for generating a transient current with the result that it is impossible to increase the sensitivity. In other words, notwithstanding the increase in the capacitance, it is necessary to increase the size of the MOSFET in order to maintain a high dv/dt capability.
FIG. 2A shows still another prior art PNPN semiconductor switch and its equivalent circuit is shown in FIG. 2B. The PNPN semiconductor switch shown in FIGS. 2A and 2B has substantially the same construction as that shown in FIGS. 1A and 1B. More particularly, a polycrystalline silicon resistor 118 is formed on the righthand side of the gate electrode 10.
The PNPN semiconductor switch shown in FIGS. 2A and 2B also manifests a high dv/dt capability. The gate sensitivity is determined by the polycrystalline silicon resistor 118 instead of the resistor 111 shown in FIG. 1A. Since it is easy to make the resistance value of resistor 118 high, it is possible to improve the gate sensitivity.
With the PNPN semiconductor switch shown in FIG. 2A, since it is necessary to form the polycrystalline silicon resistor 118 on the P type diffused layer 2 the area thereof is increased so that the capacitance between the P type diffused region 2 and the N type substrate 16 increases, thus creating a large transient current. Consequently, in order to maintain a large dv/dt capability, it is necessary to provide a large MOSFET.
Although it is possible to form the polycrystalline silicon resistor 118 on the outside of the P type diffused region 2, a transient current would be created due to a capacitance between the wiring interconnecting the resistor 118 and the electrode 10 and interconnecting the semiinsulating layer 12 and the N type substrate 16 via the insulating layer 11 so that it is necessary to provide a large MOSFET for the purpose of maintaining a high dv/dt capability.
In addition, where the sensitivity of the PNPN semiconductor switches shown in FIGS. 1A and 2A is made too high, misoperation would result when a low peak voltage which is lower than the threshold voltage of the MOSFET but builds up sharply is applied. For this reason, there is a limit for the sensitivity.
For the purpose of increasing the gate sensitivity of a photo PNPN semiconductor switch, a circuit has been proposed in which a photo current is amplified by a phototransistor and then supplied to the gate electrode of the PNPN element. FIG. 4 shows one example of the simplest circuit comprising a PNPN element 21, an anode terminal 22, cathode terminal 23, a N gate terminal 24, a P gate terminal 25, and a phototransistor 26.
In this circuit, when a positive bias is applied to the anode terminal 22 and a negative bias is applied to the cathode terminal 23 and when light is irradiated upon the phototransistor 26, a current which is amplified by the phototransistor 26 flows into the P gate terminal of the PNPN element 21 from the anode terminal 22 through the N gate terminal 24, thus turning ON the PNPN switch 21. Accordingly, its gate sensitivity is high.
However, when a steeply building up voltage is impressed across the anode terminal 22 and a cathode terminal 23, a transistor current formed at the base junction of the NPN phototransistor 26 is greatly amplified by its amplifying function and then flows into the P gate terminal 25 of the PNPN element 21, thus greatly impairing the dv/dt capability of the switching element.
Even when the PNPN element 21 is replaced by the PNPN element which is shown in FIG. 1A and which has a large dv/dt capability, it is necessary to use a complicated PNPN element having an MOS construction capable of passing an extremely large transient current so as to prevent dv/dt misoperation.